
Altera Corporation 31
MAX 7000 Programmable Logic Device Family Data Sheet
Tables 19 through 26 show the MAX 7000 and MAX 7000E AC
operating conditions.
Table 19. MAX 7000 & MAX 7000E External Timing Parameters Note (1)
Symbol Parameter Conditions -6 Speed Grade -7 Speed Grade Unit
Min Max Min Max
t
PD1
Input to non-registered output C1 = 35 pF 6.0 7.5 ns
t
PD2
I/O input to non-registered output C1 = 35 pF 6.0 7.5 ns
t
SU
Global clock setup time 5.0 6.0 ns
t
H
Global clock hold time 0.0 0.0 ns
t
FSU
Global clock setup time of fast input (2) 2.5 3.0 ns
t
FH
Global clock hold time of fast input (2) 0.5 0.5 ns
t
CO1
Global clock to output delay C1 = 35 pF 4.0 4.5 ns
t
CH
Global clock high time 2.5 3.0 ns
t
CL
Global clock low time 2.5 3.0 ns
t
ASU
Array clock setup time 2.5 3.0 ns
t
AH
Array clock hold time 2.0 2.0 ns
t
ACO1
Array clock to output delay C1 = 35 pF 6.5 7.5 ns
t
ACH
Array clock high time 3.0 3.0 ns
t
ACL
Array clock low time 3.0 3.0 ns
t
CPPW
Minimum pulse width for clear and
preset
(3) 3.0 3.0 ns
t
ODH
Output data hold time after clock C1 = 35 pF (4) 1.0 1.0 ns
t
CNT
Minimum global clock period 6.6 8.0 ns
f
CNT
Maximum internal global clock
frequency
(5) 151.5 125.0 MHz
t
ACNT
Minimum array clock period 6.6 8.0 ns
f
ACNT
Maximum internal array clock
frequency
(5) 151.5 125.0 MHz
f
MAX
Maximum clock frequency (6) 200 166.7 MHz
Kommentare zu diesen Handbüchern