Cadence Q DRIVE SERIES Bedienungsanleitung PDF herunterladen (Seite 6)

B. Timing Verification

(i) Prepare the “timing verification” template for timing verification tool,

“timing.tcl”

You need to generate another template in your synthesis directory for timing verification

after synthesizing your Verilog module(s) in order to see timing violations that this

synthesized circuit may have caused. The following timing.tcl file is a very basic file to

execute timing verification.

timing.tcl file:

proc timing { } {

# Defining an ideal clock

# ******************

# -waveform {leading_edge trailing_edge}

# -period: the value of the period

# "ideal_clock" is the name of the clock

# -clock: specifies the name of the ideal clock

# -pos: the positive edge of the ideal clock

# -neg: the negative edge of the ideal clock

# *********************************

set_clock ideal_clock -waveform {0 4} -period 10

set_clock_root -clock ideal_clock -pos module_clock

# Source all_inputs

# **************

proc all_inputs {} {find -port -input -noclocks "*"}

# Source all_outputs

# ***************

proc all_outputs {} {find -port -output "*"}

# Defining the set-up and hold times for all input(s) with respect to ideal_clock

# -early refers to a set-up time value for your input(s)

# -late refers to a hold-time value for your input(s)

# ***************************************

set_input_delay -clock ideal_clock -early 0.1 [all_inputs]

set_input_delay -clock ideal_clock -late 0.2 [all_inputs]

# Defining the set-up time for the next module's input ports

set_external_delay 0.0 -clock ideal_clock [all_outputs]

# Defining the drive (output) resistance of your input(s)

set_drive_resistance 0 [all_inputs]

}

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Cadence Q DRIVE SERIES Bedienungsanleitung Seite 6